There is known in the art a carry-forming unit (cf., U.S. Pat. No. 3,728,532 of April 1973, class G 06 F 7/06) comprising two gate circuits and an inverter and having two inputs, a control input and an output. A first one of said two inputs is connected to the carry input and a second one--to the operand bit input, and the control input is connected to the output of an exclusive OR-circuit of the adding circuit. The output of the carry-forming unit is connected to the carry output.
Said prior art unit features a low speed and is hard to implement inasmuch as it employs transistors of complementary types (C-MOSFET).
Closest to the herein disclosed carry-forming unit by its technical solution is a prior art carry-forming unit (cf., U.S. Pat. No. 4,016,546 of 1977, class 340/172.5) comprising a first MOSFET transmitting a signal from a carry input to a carry output of the carry-forming unit, a second MOSFET for resetting the carry-forming unit and a first inverter for shaping at the carry output a signal of carry from a given bit, the input of said inverter being connected to the input of first preparatory function of the carry-forming unit while the output of the first inverter and the drain of the first MOSFET are connected to the carry output of the carry-forming unit, and the gate of the first MOSFET is connected to the input of second preparatory function of the carry-forming unit. The sources of the first and second MOSFET's are connected to the carry input of the carry-forming unit, the drain of the second MOSFET is connected to a power supply line, and the gate of the second MOSFET and pulse input of the first inverter are connected to a clock signal line.
Under conditions of a high bit capacity of numbers being processed, such a carry-forming unit is incapable of ensuring a high speed inasmuch as, in the worst case of a complete carry, the signal passes through series-connected MOSFET's presenting a distributed R-C circuit the delay in which increases with the bit capacity.